A delay locked loop circuit (DLL: Delay Locked Loop) generates a multi-phase clock synchronized in phase with an input clock. The DLL includes: a delay circuit capable of variably controlling a delay time which is a propagation time of the input clock; a phase comparator which compares the phase of a propagation clock propagated through the delay circuit with the phase of the input clock, to output a signal corresponding to the phase difference; a charge pump which generates either a charge current or a discharge current according to the output of the phase comparator; and a capacitor which is charged or discharged by the current of the charge pump. The voltage of the capacitor is fed back to the delay circuit as a control voltage for the delay circuit.
In the DLL, when synchronized in phase, a propagation clock propagated through the delay circuit is delayed for one period (360°) from the input clock. Therefore, N delay buffers constituting the delay circuit generates multi-phase clocks of which phases are 1 to N-times of 360°/N of the input clock, respectively.
In the patent literatures of Japanese Laid-open Patent Publication No. Hei-10 (1998)-79663 and Japanese Laid-open Patent Publication No. 2002-43934, descriptions are given on the DLL. Also, a description is given on the PLL in the patent literature Japanese Laid-open Patent Publication No. 2003-179470.
As described above, in the DLL, the delay circuit delays the input clock for one period thereof. Therefore, the delay amount of the delay circuit is needed to be differentiated when the input clock frequency differs.
However, there is a demand that a high-speed transmission system using the DLL be operable through a wide range of a transmission rate to be compatible, from a legacy low-speed transmission system of around Gbps to a high-speed transmission system of several Gbps. Therefore, the delay circuit in the DLL is also demanded to be compatible with a wide frequency range.